CMOS Nanoelectronics: Innovative Devices, Architectures, and by Nadine Collaert

By Nadine Collaert

This booklet covers some of the most vital gadget architectures which have been extensively researched to increase the transistor scaling: FinFET. beginning with thought, the e-book discusses the benefits and the combination demanding situations of this gadget structure. It addresses intimately the subjects similar to high-density fin patterning, gate stack layout, and source/drain engineering, that have been thought of demanding situations for the mixing of FinFETs. The booklet additionally addresses circuit-related features, together with the influence of variability on SRAM layout, ESD layout, and high-T operation. It discusses a brand new equipment thought: the junctionless nanowire FET.

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Extra info for CMOS Nanoelectronics: Innovative Devices, Architectures, and Applications

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41. , Cleavelin C. -S. and Colinge J. , “Improvement of FinFET electrical characteristics by hydrogen annealing,” IEEE Electron. Device Lett, 25(8), 541–543, 2004. 42. , Hussain M. , Harris H. , Jammy R. and Thompson S. , “Comparison of uniaxial wafer bending and contact-etch-stop-liner stress induced performance enhancement on double-gate FinFETs,” IEEE Electron. Device Lett, 29(5), 480–482, 2008. 43. , Anil K. , Jurczak M. , “Performance improvement of tall triple gate devices with strained SiN layers,” IEEE Electron.

For example, on a multigated architecture, the dry etching process for patterning fins with 25 nm CD and 65 nm height on a relaxed 350 nm fin pitch was relatively easily transferred to a 200 nm fin pitch [1]. However, this process could not be transferred to a 124 nm fin pitch (32 nm). In order to obtain fins with 23 nm CD we had to tune the PR trim, the DARC opening and the HM patterning [6]. Moreover, it was observed that this process could not be straightforwardly applied to a 90 nm fin pitch (22 nm node).

However, the quantum confinement, which is a result of the aggressive scaling of the channel diameter, leads to an unwanted increase in threshold voltage [59]. The carriers in the channel start to occupy discrete energy levels where the lowest energy level is located at a higher level than the bottom of the conduction band. This is different from the traditional continuum of energy levels or bands found in bulk materials. As such, more band bending is required to form the inversion layer in the channel.

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